8V97051 Datasheet, PDF (10/56 Pages) Integrated Device Technology – Dual Differential Outputs

8V97051 DATA SHEET
FROM VCO OUTPOUT
or FROM M0 OUTPUT
N counter
3^rd Order
ΣΔ Modulator
TO PFD
same channelization. Using the doubler may offer better phase noise
performance. The high resolution Modulus also allows to use the
same input reference frequency to achieve different channelization
requirements. Using a unique PFD frequency for several needed
channelization requirements allows the user to design a loop filter for
the different needed setups and ensure the stability of the loop.
The channelization is given by
(4)
12 Bit FRAC
+ ^{16 Bit INT}
12 Bit MOD
Figure 1. RF Feedback N Divider
In low noise mode (dither disabled), the Sigma Delta modulator can
generate some fractional spurs that are due to the quantization noise.
The spurs are located at regular intervals equal to f_PFD/L where L is
the repeat length of the code sequence in the Sigma Delta modulator.
That repeat length depends on the MOD value, as described in Table
4B.
The 16 INT bits (Bit[D30:D15] in Register 0) set the integer part of the
feedback division ratio.
The 12 FRAC bits (Bit[D14:D3] in Register 0) set the numerator of the
fraction that goes into the Sigma Delta modulator. FRAC can be
extended to 16-bits using the EXT_FRAC bits in Register 7.
The 12 MOD bits (Bit[D14:D3] in Register 1) set the denominator of
the fraction that goes into the Sigma Delta modulator. MOD can be
extended to 16-bits using the EXT_MOD bits in Register 7.
From the relation (2), the VCO minimum step frequency is
determined by (1/MOD) * f_PFD.
FRAC values from 0 to (MOD – 1) cover channels over a frequency
range equal to the PFD reference frequency.
The PFD frequency is calculated as follows:
(3)
Use 2R instead of R if the Reference Divide by 2 is used. 
REF_CLK = the input reference frequency (REF_IN)
D
= the input reference doubler (0 if not active or 1 if active)
R
= the 10-Bits programmable input reference pre-divider
The programmable modulus (MOD) is determined based on the input
reference frequency (REF_IN) and the desired channelization (or
output frequency resolution). The high resolution provided on the R
counter and the Modulus allows the user to choose from several
configuration (by using the doubler or not) of the PLL to achieve the
Table 4B. Fractional Spurs Due to the Quantization Noise
Condition (Dither Disabled) L
Spur intervals
MOD can be divided by 2, 
but not by 3
2 x MOD f_PFD/(2*MOD)
MOD can be divided by 3, 
but not by 2
3 x MOD f_PFD/(3*MOD)
MOD can be divided by 6
Other conditions
6 x MOD
MOD
f_PFD/(6*MOD)
f_PFD/MOD
(channel step)
In order to reduce the spurs, the user can enable the dither function
to increase the repeat length of the code sequence in the Sigma
Delta modulator. The increased repeat length is 2²¹ cycles so that the
resulting quantization error is spread to appear like broadband noise.
As a result, the in-band phase noise may be degraded when using
the dither function.
When the application requires the lowest possible phase noise and
when the loop bandwidth is low enough to filter most of the
undesirable spurs, or if the spurs won’t affect the system
performance, it is recommended to use the low noise mode with
dither disabled.
LOW POWER WIDEBAND FRACTIONAL RF SYNTHESIZER / PLL
10
REVISION 3 07/30/15