8V97051 Datasheet, PDF (16/56 Pages) Integrated Device Technology – Dual Differential Outputs

8V97051 DATA SHEET
3- or 4-Wire SPI Interface Description
The 8V97051 has a serial control port capable of responding as a
slave in an SPI compatible configuration to allow access to any of the
internal registers (see section, “Register Map” on page 17) for device
programming or examination of internal status. See the specific
sections for each register for details on meanings and default
conditions.
SPI mode slave operation requires that a device external to the
8V97051 has performed any necessary serial bus arbitration and/or
address decoding at the level of the board or system. The 8V97051
begins a cycle by detecting an asserted (low) state on the nCS input
at a rising edge of SCLK. This is also coincident with the first bit of
data being shifted into the device. In SPI mode, the first bit is the Most
Significant Bit (MSB) of the data word being written. Data must be
written in 32-bit words, with nCS remaining asserted and one data bit
being shifted in to the 8V97051 on every rising edge of SCLK. If nCS
is de-asserted (high) at any time except after the complete 32^nd SCLK
cycle, this is treated as an error and the shift register contents are
discarded. No data is written to any internal registers. If nCS is
de-asserted (high) as expected at a time at least t_SU after the 32^nd
falling edge of SCLK, then this will result in the shift register contents
being acted on according to the control bit in it.
It is recommended to write the registers in reverse sequential order,
starting with the highest register number first and ending with
Register 0.
The word format of the 32-bit quantity in the shift register is shown in
Table 4F. The register fields in the 8V97051 have been organized so
that the three LSBs in each 32-bit register row are not used for data
transfer. These bits will represent the base address for the 32-bit
register row.
To perform a register Read, the user needs set the MUX_OUT bits
(Bits[28:D26]) in Register 2 to 111 to configure the MUX_OUT pin as
SDO. Register 7 (Instruction register) needs to be set for Read
operation. Bit D3 of Register 7 will set the Read or Write command,
and Bits[D4:D6] determine the read back address.
If a read operation is requested, 32-bits of read data will be provided
in the immediately subsequent access. nCS must be de-asserted
(high) for at least t_PW, and then reasserted (low).
If SCLKE = 1 (default condition), one data bit will be transmitted on
the SDO output at the falling edge of nCS and each falling edge of
SCLK as long as nCS remains asserted (low), and the master device
should capture data on the rising edge of SCLK. If SCLKE = 0, one
data bit will be transmitted on the SDO output at each rising edge of
SCLK as long as nCS remains asserted (low), and the master device
should capture data on the falling edge of SCLK.
If nCS is de-asserted (high) before 32-bits of read data have been
shifted out, the read cycle will be considered to be completed. If nCS
remains asserted (low) longer than 32-bit times, then the data during
those extra clock periods will be undefined. The MSB of the data will
be presented first.
Table 4F. SPI Mode Serial Word Structure
MSB
Bit #
31
…
5
4
3
Meaning
D[31:3]
Width
29
LSB
2
1
0
Control Bits
3
LOW POWER WIDEBAND FRACTIONAL RF SYNTHESIZER / PLL
16
REVISION 3 07/30/15