8V97051 Datasheet, PDF (17/56 Pages) Integrated Device Technology – Dual Differential Outputs

Register Map
Register 0
Table 5A. Register 0 Bit Allocation
8V97051 DATA SHEET
FEEDBACK DIVIDER INTEGER VALUE (INT)
FEEDBACK DIVIDER FRACTIONAL VALUE CONTROL
(FRAC)
BITS
Table 5B. Register 0: 16-Bit Feedback Divider Integer Value (INT). Function Description
Name
Description
Factory Default
Function
NDiv[16:1] Feedback Divider Integer Value (INT)
0000 0000 0110 0100
(INT = 100)
0000 0000 0000 0000 = Not allowed
0000 0000 0000 0001 = Not allowed
...
0000 0000 0000 0111 = Not allowed
0000 0000 0000 1000 = 8
…
0000 0000 0001 0111 = 23
0000 0000 0001 1000 = 24
…
1111 1111 1111 1111 = 65,535
Table 5C. Register 0: 12-Bit Feedback Divider Fractional Value (FRAC). Function Description¹
Name
Description
Factory Default
Function
FDiv[12:1]
0000 0000 0000
Feedback Divider Fractional Value (FRAC)
(FRAC = 0)
0000 0000 0000 = 0
0000 0000 0001 = 1
…
1111 1111 1111 = 4095
NOTE 1. This table is used when bit 16b_12b_sel is set to 0 (default). If the 16b_12b_sel is set to 1, refer to Table 12J, Page 33.
REVISION 3 07/30/15
17
LOW POWER WIDEBAND FRACTIONAL RF SYNTHESIZER / PLL