8V97051 Datasheet, PDF (12/56 Pages) Integrated Device Technology – Dual Differential Outputs

8V97051 DATA SHEET
Figure 3. Output Clock Distribution
RF_OUT and nRF_OUT are derived from the drain of an NMOS
differential pair driven by the VCO output (or by the M0 Divider), as
shown in Figure 4, Output Stage.
RF_OUT nRF_OUT
÷ M0
Figure 5. Broadband Matching Termination
This termination scheme allows to provide one of the selected output
power on the differential pair when connected to a 50 load. (See the
RF Output Power section for more information about the output
power selection).
The 50 resistor connected to V_DDA can also be replaced by a
choke, for better performance and optimal power transmission.
The pull up inductor value is frequency dependent. For impedance 
of 50 pull-up, the inductance value can be calculated as 
L = 50/(2*3.14*F), where F is operating frequency. In this example, 
L = 3.9nF is for an operating frequency of approximately 2GHz.
Figure 4. Output Stage
Eight programmable output power levels can be programmed from
-4dBm to +7dBm (see RF Output Power section).
The 8V97051 offers an auxiliary output (RF_OUT_B). If the auxiliary
output stage is not used, it can be powered down by using the
RF_OutB_En bit in Register 4.
The supply current to the output stage can be shut down until the part
achieves lock. To enable this mode, the user will set the MTLD bit in
Register 4. The MUTE pin can be used to mute all outputs and be
used as a similar function.
Output Matching
The outputs of the 8V97051 are Open Drain Output and can be
matched in different ways.
A simple broadband matching is to terminate the open drain
RF_OUT output with a 50 to V_DDA, and with an AC coupling
capacitor in series. An example of this termination scheme is shown
on Figure 5, Broadband Matching Termination.
Figure 6. Optimal Matching Termination
See Applications Information section for more recommendations on
the termination scheme.
Band Selection Disable
For a given frequency, the output phase can be adjusted when using
the Band_Sel_Disable bit (Bit D28 in Register 1). When this bit is
enabled (Bit D28 set to 1), the part does not do a VCO band selection
or phase resync after an update to Register 0.
When the Band_Sel_Disable bit is set to 0, and when Register 0 is
updated, the part proceeds to a VCO band selection, and to a phase
resync if phase_resync is also enabled in Register 3 (Bits[D16:D15]
set to D16 = 1 and D15 = 0).
The “Band_Sel_Disable” bit is useful when the user wants to make
small changes in the output frequency (<1MHz from the nominal
frequency) without recalibrating the VCO and minimizing the settling
time.
LOW POWER WIDEBAND FRACTIONAL RF SYNTHESIZER / PLL
12
REVISION 3 07/30/15