ICS9EX21801A Datasheet, PDF (3/14 Pages) Integrated Device Technology – 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
Datasheet
Pin Description
PIN #
PIN NAME
1 VDD
2 OE10#
3 DIF_10
4 DIF_10#
5 OE11#
6 DIF_11
7 DIF_11#
8 OE12#
9 DIF_12
10 DIF_12#
11 GND
12 VDD
13 DIF_13
14 DIF_13#
15 OE13#
16 DIF_14
17 DIF_14#
18 OE14#
19 DIF_15
20 DIF_15#
21 VDD
22 OE15_17#
23 DIF_16
24 DIF_16#
25 DIF_17
26 DIF_17#
27 IREF
28 GNDA
29 VDDA
30 CLKA_IN
31 CLKA_IN#
32 GND
33 CLKB_IN
34 CLKB_IN#
35 VDD
36 OE_01234#
PIN TYPE
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
IN
OUT
OUT
OUT
OUT
OUT
PWR
PWR
IN
IN
PWR
IN
IN
PWR
IN
DESCRIPTION
Power supply, nominal 3.3V
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Active low input for enabling DIF pairs 15, 16 and 17
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475
ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
True Input for differential reference clock.
Complement Input for differential reference clock.
Ground pin.
True Input for differential reference clock.
Complement Input for differential reference clock.
Power supply, nominal 3.3V
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
IDT^TM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
3
1463B — 01/20/10