ICS9EX21801A Datasheet, PDF (2/14 Pages) Integrated Device Technology – 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux

ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
Pin Configuration
Datasheet
VDD
OE10#
DIF_10
DIF_10#
OE11#
DIF_11
DIF_11#
OE12#
DIF_12
DIF_12#
GND
VDD
DIF_13
DIF_13#
OE13#
DIF_14
DIF_14#
OE14#
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
2
3
4
5
6
7
8
9
10
9EX21801AKLF
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 DIF_6#
53 DIF_6
52 OE6#
51 DIF_5#
50 DIF_5
49 OE5#
48 DIF_4#
47 DIF_4
46 DIF_3#
45 DIF_3
44 GND
43 VDD
42 DIF_2#
41 DIF_2
40 DIF_1#
39 DIF_1
38 DIF_0#
37 DIF_0
72-pin MLF
Frequency/Functionality Table
Byte 0,
bit 2
Byte 0,
Byte 0,
(100_133M#
bit 1
bit 0
Latch)
FSB
FSA
1
0
1
0
0
1
0
1
1
0
1
0
0
0
0
1
0
0
1
1
0
1
1
1
Input
MHz
100.00
133.33
166.67
200.00
266.67
333.33
400.00
DIF_x
MHz
100.00
133.33
166.67
200.00
266.67
333.33
400.00
Reserved
Notes
1
1
2
2
2
2
2
Notes:100M_133M#
1. Latch selects between 100 and 133 MHz.
This is equivalent to FSC in CK410B+/CK509B FS table.
2. Writing Byte 0 bits (2:0) can select other frequencies.
These frequencies are not characterized in PLL Mode
HIBW_BYPM_LOBW# Selection (Pin 63)
State
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.0V
Mode
Low BW
Bypass
High BW
IDT^TM 18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
Power Groups
Pin Number
VDD
GND
29
28
1,12,21,35,43,55 11,32,44
Description
Main PLL, Analog
DIF clocks
Power Down Functionality
INPUTS
OUTPUTS
CKPWRGD/PD#
1
Input
Running
DIF_x
Running
0
X
Hi-Z
PLL State
ON
OFF
SMBus Address Selection (pins 66, 67)
SMB_A1
0
0
1
1
SMB_A0
0
1
0
1
Address
D4
D6
D8
DA
1463B — 01/20/10
2