ICS932SQ420DGLF Datasheet, PDF (3/27 Pages) Integrated Device Technology – PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
Pin Descriptions - 64 TSSOP
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PIN N AME
SMBCLK
GN D14
AVDD14
VDD1 4
vRE F14_ 3x/ TE ST_S EL
GN D14
GN DXTAL
X1_ 25
X2_ 25
VDDXTAL
GN DPCI
VDDPCI
PCI4 _2x
PCI3 _2x
PCI2 _2x
PCI1 _2x
PCI0 _2x
GN DPCI
VDDPCI
VDD4 8
^48M _2x/100 M_13 3M#
GN D48
GN D96
DO T9 6T
DO T9 6C
AVDD96
TEST_ MO DE
CKP WRG D# /PD
VDDSRC
TYPE
DESCRIPTION
IN Clock pin of SMBUS circuitry, 5V tolerant
PWR Ground pin for 14MHz output and logic.
PWR Analog power pin for 14MHz PLL
PWR Pow er pin for 14MHz output and logic
I/O
14.318 MH z reference clock. 3X drive strength as default / TEST_SEL latched input to enable test mode.
Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down.
PWR Ground pin for 14MHz output and logic.
PWR Ground pin for Crystal Oscillator.
IN Crystal input, Nominally 25.00MHz.
OUT Crystal output, Nominally 25.00MHz.
PWR 3.3V power for the crystal oscillator.
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
PWR 3.3V power for the 48MHz output and logic
3.3V 48MHz output/ 3.3V tolerant CPU frequency select latched input pin. See VilFS and VihFS values for
I/O thresholds. This pin has a weak (~120Kom) internal pull up.
1 = 100MHz, 0 = 133MHz operating frequency
PWR Ground pin for 48MHz output and logic.
PWR Ground pin for DOT96 output and logic.
True clock of differential 96MHz output. These are current mode outputs. These are current mode outputs
OUT _{and external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.}
Complementary clock of differential 96MHz output. These are current mode outputs and external 33 ohm
OUT _{series resistors and 49.9 ohm shunt resistors are required for termination.}
PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
IN ^{TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to}
Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an
IN asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs
are stopped.
PWR 3.3V power for the SRC outputs and logic
30 SRC0T
OUT ^{True clock of differential SRC output. These are current mode outputs. These are current mode outputs and}
external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.
31 SRC0C
32 GN DSRC
33 SRC1C
OUT ^{Complementary clock of differential SRC output. These are current mode outputs and external 33 ohm}
series resistors and 49.9 ohm shunt resistors are required for termination.
PWR Ground pin for SRC outputs and logic.
OUT
Complementary clock of differential SRC output. These are current mode outputs and
series resistors and 49.9 ohm shunt resistors are required for termination.
external 33 ohm
34 SRC1T
OUT
True clock of differential SRC output. These are current mode outputs. These are current mode outputs and
external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.
35 SRC2C
OUT
Complementary clock of differential SRC output. These are current mode outputs and
series resistors and 49.9 ohm shunt resistors are required for termination.
external 33 ohm
36 SRC2T
OUT
True clock of differential SRC output. These are current mode outputs. These are current mode outputs and
external 33 ohm series resistors and 49.9 ohm shunt resistors are required for termination.
37 VDDSRC
38 AVDD_SRC
39 GN DSRC
40 IREF
PWR 3.3V power for the SRC outputs and logic
PWR 3.3V power for the SRC PLL analog circuits
PWR Ground pin for SRC outputs and logic.
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a
OUT fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard
va lue .
IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
3
932SQ420D
REV H 042012