9DBV0531_17 Datasheet, PDF (3/17 Pages) Integrated Device Technology – 5-Output 1.8V HCSL Fanout Buffer

9DBV0531 DATASHEET
Pin Descriptions
Pin# Pin Name
1 vOE4#
2 DIF4
3 DIF4#
4 VDDR1.8
5 CLK_IN
6 CLK_IN#
7 GNDR
8 GNDDIG
9 VDDDIG1.8
10 SCLK_3.3
11 SDATA_3.3
12 vOE0#
13 DIF0
14 DIF0#
15 GND
16 VDDO1.8
17 vOE1#
18 DIF1
19 DIF1#
20 GND
21 VDDO1.8
22 DIF2
23 DIF2#
24 vOE2#
25 VDDO1.8
26 GND
27 DIF3
28 DIF3#
29 vOE3#
30 GND
31 ^CKPWRGD_PD#
32 ^SADR_tri
33 ePAD
Type Pin Description
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT
PWR
IN
IN
Differential Complementary clock output
1.8V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
GND
GND
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
PWR
IN
1.8V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
IN
OUT
OUT
Data pin for SMBus circuitry, 3.3V tolerant.
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
GND
PWR
Ground pin.
Power supply for outputs, nominally 1.8V.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT
OUT
Differential true clock output
Differential Complementary clock output
GND
PWR
Ground pin.
Power supply for outputs, nominally 1.8V.
OUT
OUT
IN
PWR
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for outputs, nominally 1.8V.
GND
OUT
Ground pin.
Differential true clock output
OUT
IN
GND
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
LATCHED IN
Tri-level latch to select SMBus Address. It has an internal 120Kohm pull down
resistor. See SMBus Address Selection Table.
GND Connect epad to ground.
MARCH 10, 2017
3
5-OUTPUT 1.8V HCSL FANOUT BUFFER