9DBV0531_17 Datasheet, PDF (16/17 Pages) Integrated Device Technology – 5-Output 1.8V HCSL Fanout Buffer

9DBV0531 DATASHEET
Ordering Information
Part / Order Number
9DBV0531AKLF
9DBV0531AKLFT
9DBV0531AKILF
9DBV0531AKILFT
Shipping Packaging
Trays
Tape and Reel
Trays
Tape and Reel
Package
32-pin VFQFPN
32-pin VFQFPN
32-pin VFQFPN
32-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev.
A
B
C
Initiator
RDW
RDW
RDW
Issue Date Description
1. Updated front page text
2. Updated block diagram
3. Updated electrical tables
7/28/2014 4. Updated test loads diagrams.
5. Updated Smbus byte 2, 3 and 6 labeling. Functionality did not
change.
6. Move to final.
8/27/2014 ^{1. Updated min Vhigh on DIF outputs from 630mV to 660mV, correcting}
a typo.
8/28/2014 ^{1. Corrected Supply Voltage in Absolute Maximum Ratings.}
2. Lowered additive phase jitter specs.
Page #
Various
7
Various
1. Revised front page text extensively.
2. Added note about Spread Spectrum Compatibility to the features.
3. Change pin names of VDDA1.8 and GNDA to VDDO1.8 and GND, to
clarify that this part does not have a PLL. Updated Power Connections
table. This is a document change only. There is no silicon change.
4. Corrected OE4# to indicate an internal pull down, not a pull up.
5. Added epad nomenclature to DS
D
RDW 3/28/2016 _{6. Updated package drawing to latest version - no package change.}
7. Replaced LVDS termination info with reference to AN-891
1-5,7,9
14
8. Update current consumption table to remove references to VDDA1.8
9. Added "RMS additive phase jitter: 251fs" to phase noise plot
10. Updated "Clock Input Parameters" table for consistency - no silicon
change.
11. Updated "Output Duty Cycle, Jitter, Skew and PLL Characteristics"
and "Phase Jitter" tables to remove references to bypass mode.
E
RDW 5/23/2016 Updated POD drawings with the latest from Doc Control
14,15
1. Removed "...Bypass Mode" reference in note 3 under Output Duty
F
RDW 3/10/2017 ^{Cycle table.}
8
2. Corrected spelling errors/typos.
3. Update Additive Phase Jitter conditions for PCIe Gen3.
5-OUTPUT 1.8V HCSL FANOUT BUFFER
16
MARCH 10, 2017