9DBV0531_17 Datasheet, PDF (11/17 Pages) Integrated Device Technology – 5-Output 1.8V HCSL Fanout Buffer

9DBV0531 DATASHEET
SMBus Table: Output Enable Register ¹
Byte 0
Name
Control Function
Type
0
Bit 7
Reserved
Bit 6
DIF OE3
Output Enable
RW
Low/Low
Bit 5
DIF OE2
Output Enable
RW
Low/Low
Bit 4
Reserved
Bit 3
DIF OE1
Output Enable
RW
Low/Low
Bit 2
Reserved
Bit 1
DIF OE0
Output Enable
RW
Low/Low
Bit 0
Reserved
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Name
Control Function
Type
0
Bit 7
Reserved
Bit 6
Reserved
Bit 5
DIF OE4
Output Enable
RW
Low/Low
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Controls Output Amplitude ^RW
RW
00 = 0.6V
10= 0.8V
1. A low on the DIF OE bit will overide the OE# pin and force the differential output Low/Low
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Bit 7
Reserved
Bit 6
SLEWRATESEL DIF3
Slew Rate Selection
Bit 5
SLEWRATESEL DIF2
Slew Rate Selection
Bit 4
Reserved
Bit 3
SLEWRATESEL DIF1
Slew Rate Selection
Bit 2
Reserved
Bit 1
SLEWRATESEL DIF0
Slew Rate Selection
Bit 0
Reserved
Type
RW
RW
RW
RW
0
Slow setting
Slow setting
Slow setting
Slow setting
SMBus Table: DIF Slew Rate Control Register
Byte 3
Name
Control Function
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
SLEWRATESEL DIF4
Reserved
Reserved
Adjust Slew Rate of DIF4
Type
RW
0
Slow setting
Byte 4 is Reserved and reads back 'hFF
1
OE# pin control
OE# pin control
OE# pin control
OE# pin control
Default
1
1
1
1
1
1
1
1
1
OE# pin control
01 = 0.7V
11 = 0.9V
Default
0
1
1
0
1
1
1
0
1
Fast setting
Fast setting
Fast setting
Fast setting
Default
1
1
1
1
1
1
1
1
1
Fast setting
Default
1
1
0
0
0
1
1
1
MARCH 10, 2017
11
5-OUTPUT 1.8V HCSL FANOUT BUFFER