ICS8714008I Datasheet, PDF (27/34 Pages) Integrated Device Technology – Output frequency range

ICS8714008I DATA SHEET
FEMTOCLOCK^® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS^TM AND ETHERNET
Logic Control Input Examples
Set Logic
Set Logic
VD D _{Input to '1'} V DD _{Input to '0'}
RU1
1K
To Logic
Input
pins
RD1
N ot I ns t all
RU2
N ot I ns t al l
To Logic
Input
pins
RD2
1K
VD D
C2
10 u F
VD D A ²
FB2
1
C3
1 0uF
B LM18BB22 1S N 1
3 .3 V
FB 1
2
1
BLM18BB 22 1SN 1
C1
0 .1uF
U1
OE_MLV DS
O E0
2
11
OE_ML VD S
O E1
O E2
12 ^OE0
13 ^OE1
O E2
MR
PL L_S EL
10
6 ^MR
PLL _SEL
FBI _D IV 0
FBI _D IV 1
FBO_D IV
15
16 ^{FB I_D I V0}
9 ^{FB I_D I V1}
FB O_D I V
PD I V0
PD I V1
QD IV0
QD IV1
QD IV2
QD IV3
QD IV4
QD IV5
QD IV6
QD IV7
55
56 ^{PD I V0}
PD I V1
20
21 ^{QD IV 0}
22 ^{QD IV 1}
23 ^{QD IV 2}
51 ^{QD IV 3}
50 ^{QD IV 4}
49 ^{QD IV 5}
48 ^{QD IV 6}
QD IV 7
T o M LV DS bus
ML VD S
nMLVD S
3
ML VD S
4
nMLV D S
OE_MLVDS = 1
to select
MLVDS output
Zo = 50 Ohm
CLK 53
R1
CLK
Zo = 50 Ohm
1 00
nCLK 54
nC LK
LVD S D riv e r
R13
49. 9
18
FB IN
17
nFBI N
R 12
49 . 9
52
V D DA
47
Q0 ₄₆
nQ0
44
Q1 ₄₃
nQ1
41
Q2 ₄₀
nQ2
39
Q3 ₃₈
nQ3
36
Q4 ₃₅
nQ4
34
Q5 ₃₃
nQ5
27
Q6 ₂₈
nQ6
24
Q7 ₂₅
nQ7
29
IR EF
8
nc
32
FBOU T
31
nFBOU T
VD D
C4
0. 1 uF
C6
C7
0.1 uF 0 .1uF
C8
0 .1 u F
C9
0. 1uF
C 10
0. 1 uF
C11
0.1 uF
V DD A
C5
0. 1u F
R6 33
R9 33
R7
50
Place each 0.1uF bypass cap directly
adjacent to its corresponding VDD or
VDDA pin.
1" to 14"
Zo = 50
0.5" to 3.5"
Z o = 50
+
Zo = 50
R4
50
Z o = 50
-
H C SL_Rec e iv er
PCI Express Add-In Card
HCSL Termination
R3 33
R2 33
Optional
R11
475
0" to 18"
Zo = 50
Zo = 50
R8
50
+
-
HC S L_R e ceiv er
R5
50 _{PCI Express}
P oi n t-to -P o i n t
Connec tion
Figure 9. ICS8714008I Schematic Example
ICS8714008DKI REVISION A NOVEMBER 25, 2013
27
©2013 Integrated Device Technology, Inc.