ICS8714008I Datasheet, PDF (21/34 Pages) Integrated Device Technology – Output frequency range

ICS8714008I DATA SHEET
FEMTOCLOCK^® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS^TM AND ETHERNET
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both signals must meet the V_PP and V_CMR input
requirements. Figures 4A to 4F show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 4A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
Figure 4A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 4B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVPECL
3.3V
3.3V
CLK
nCLK
Differential
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 4C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
*R3
*R4
HCSL
3.3V
CLK
nCLK
Differential
Input
Figure 4D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
3.3V
MLVDS
Zo = 50Ω
R2
100Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 4E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
ICS8714008DKI REVISION A NOVEMBER 25, 2013
Figure 4F. CLK/nCLK Input Driven by a
3.3V MLVDS Driver
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©2013 Integrated Device Technology, Inc.