ICS8714008I Datasheet, PDF (26/34 Pages) Integrated Device Technology – Output frequency range

ICS8714008I DATA SHEET
FEMTOCLOCK^® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS^TM AND ETHERNET
Schematic Example
Figure 9 (next page) shows an example ICS8714008DI application
schematic. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure the logic
control inputs are properly set. Input and output terminations shown
are also intended as examples only and may not represent the exact
user configuration.
In this particular schematic the MLVDS port is in output mode,
configured by setting OE_MLVDS = 1. Since the zero delay function
is local to the chip, the FBOUT to FBIN connection is a special case
of a point to point PCIe link. The close proximity of these two ports
means that the 33 series resistors are not necessary and the 49.9
termination resistors are to be placed at the FBIN port.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS8714008DI provides
separate VDD, VDDO and VDDA power supplies to isolate any high
switching noise from coupling into the internal PLL.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1µF capacitors be placed on the device side
of the PCB as close to the power pins as possible. This is
represented by the placement of these capacitors in the schematic.
If space is limited, the ferrite bead, 10µF and 0.1µF capacitors
connected to 3.3V can be placed on the opposite side of the PCB. If
space permits, place all filter components on the device side of the
board.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
ICS8714008DKI REVISION A NOVEMBER 25, 2013
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©2013 Integrated Device Technology, Inc.