ICS8714008I Datasheet, PDF (2/34 Pages) Integrated Device Technology – Output frequency range

ICS8714008I DATA SHEET
FEMTOCLOCK^® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESS^TM AND ETHERNET
Block Diagram
MR¹
PDIV1
PDIV0
CLK
nCLK
MR¹
OE_MLVDS
MLVDS
nMLVDS
Pulldown
Pulldown
Pulldown
Pulldown
PU/PD
Pulldown
Pullup
PDIV1:0
00 ÷4 (default)
01 ÷5
10 ÷8
11 ÷1
FBI_DIV1
FBI_DIV0
FBIN
nFBIN
Pullup
Pullup
Pulldown
PU/PD
MR¹
Pulldown
PLL_SEL
MR¹
Pullup
Pulldown
FBI_DIV1:0
00 ÷1
01 ÷2
10 ÷4
11 ÷5 (default)
QDIV0
0 ÷4 (default)
1 ÷5
3
OE2:0 (PU:PU)
QDIV0 (PD)
Q0
nQ0
0
PD
VCO
490-660MHz ¹
QDIV7
0 ÷4 (default)
1 ÷5
FBO_DIV
0 ÷4 (default)
1 ÷5
8 total HCSL Output pairs
QDIV7 (PD)
Q7
nQ7
FBO_DIV (PD)
FBOUT
nFBOUT
IREF
1_{One Master Reset pin (MR) is used to reset all the internal dividers, but the MR lines are not drawn as all tied together to reduce control line clutter, making the block diagram}
easier to read.
PU means internal pull-up resistor on pin (power-up default is HIGH if not externally driven)
PD means internal pull-down resistor on pin (power-up default is LOW if not externally driven)
ICS8714008DKI REVISION A NOVEMBER 25, 2013
2
©2013 Integrated Device Technology, Inc.