932SQ420DGLFT Datasheet, PDF (22/27 Pages) Integrated Device Technology – PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
Test Clarification Table
Comments
HW
SW
Power-up w/ TEST_SEL = 1 (>2.0V) to enter test mode.
Cycle power to disable test mode.
If TEST_SEL HW pin is 0 during power-up,
test mode can be selected through B6b6.
If test mode is selected by B6b6, then B6b7
is used to select HI-Z or REF/N.
TEST_Mode pin is not used.
Cycle power to disable test mode.
TE ST
TEST_SEL ^TEST_MODE ENTRY BIT
HW PIN HW PIN
B6b6
0
X
0
1
0
X
1
0
X
1
1
X
1
1
X
0
X
1
0
X
1
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
REF/N or
HI-Z
B6b7
X
0
1
0
1
0
1
OUTPUT
NORMAL
HI-Z
REF/N
REF/N
REF/N
HI-Z
REF/N
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θ_JA Still air
θ_JA 1 m/s air flow
θ_JA 2 m/s air flow
Thermal Resistance Junction to Case θ_JC
Thermal Resistance Junction to
θ_JB
Board
Min.
Typ.
68.2
63.3
59.6
32.5
51.5
Max.
Units
° C/W
° C/W
° C/W
° C/W
° C/W
IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
22
932SQ420D
REV H 042012