932SQ420DGLFT Datasheet, PDF (10/27 Pages) Integrated Device Technology – PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
Electrical Characteristics - Input/Supply/Common Parameters
TA = T_COM; Supply Voltage VDD = 3.3 V +/-5%
PA RAM ETER
SYMBOL
C OND ITIONS
Ambient Operating
Tempe ra ture
Input High Voltage
Input Low Voltage
T_COM
V_IH
V_IL
Commmercial range
Single-ended inputs, except
SMBus, low threshold and tri-
level inputs
Single-ended inputs, except
SMBus, low threshold and tri-
level inputs
MIN
0
2
GND - 0.3
TYP
MAX
70
UNITS NOTES
°C
1
V_DD + 0.3
V
1
0 .8
V
1
I_IN
Single-ended inputs,
V_IN = GND, V_IN = VDD
-5
5
uA
1
Input Current
Single-ended inputs.
V_IN = 0 V; Inputs with internal pull-
I_INP
up resistors
-2 00
V_IN = VDD; Inputs w ith internal
pull-dow n resistors
200
uA
1
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Input Frequency
Pin Inductance
C apac it anc e
Clk Stabilization
SS Modulation Frequency
Tdriv e_ PD#
Tfall
Trise
V_{IH _F S}
V_{IL_F S}
F_i
L_{p in}
C_IN
C_{OU T}
C_{IN X}
T_STAB
f_{M OD IN}
t_{DR VPD}
t_F
t_R
3.3 V +/-5%
0.7
V_DD + 0.3 V
1
3.3 V +/-5%
V_SS - 0.3
25.0 0
Logic Inputs
Output pin capacitance
X1 & X2 pins
From V_DD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
30
Differential output enable after
PD# de-assertion
Fall time of control inputs
Rise time of control inputs
31.50 0
200.0 00
0. 35
V
1
M Hz
2
7
nH
1
5
pF
1
5
pF
1
5
pF
1
1 .8
ms
1,2
33
kHz
1
300
us
1,3
5
ns
1,2
5
ns
1,2
SMBus Input Low Voltage
V _{ILS MB}
0.8
V
1
SMBus Input
High Voltage
V_{IH SMB}
2.1
SMBus Output
Low Voltage
V_{O LS MB}
@ I_{PUL LUP}
SMBus Sink Current
I_{PU LLU P}
@ V_OL
4
N ominal Bus Voltage
V_{DDSM B}
3V to 5V +/- 10%
2.7
SCLK/SDATA Rise Time
t_{R SMB}
(Max VIL - 0.15) to (Min VIH +
0.15 )
SCLK/SDATA Fall Time
t _FSMB
(Min VIH + 0.15) to (Max VIL -
0.15 )
SMBus Operating
Frequ enc y
f_MAXSMB
Maximum SMBus operating
frequ enc y
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
V_{D DSM B}
V
1
0.4
V
1
mA
1
5.5
V
1
1000
ns
1
300
ns
1
100
kHz
1
IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
10
932SQ420D
REV H 042012