932SQ420DGLFT Datasheet, PDF (2/27 Pages) Integrated Device Technology – PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

932SQ420D
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
Pin Configuration - 64TSSOP
SMBCLK 1
64 SMBDAT
GND14 2
63 VDDCPU
AVDD14 3
62 CPU3T
VDD14 4
v_{REF14_3x/TEST_SEL 5}
61 CPU3C
60 CPU2T
GND14 6
59 CPU2C
GNDXTAL 7
58 GNDCPU
X1_25 8
57 VDDCPU
X2_25 9
56 CPU1T
VDDXTAL 10
55 CPU1C
GNDPCI 11
54 CPU0T
VDDPCI 12
53 CPU0C
PCI4_2x 13
52 GNDNS
PCI3_2x 14
51 AVDD_NS_SAS
PCI2_2x 15
50 NS_SAS1T
PCI1_2x 16
49 NS_SAS1C
PCI0_2x 17
48 NS_SAS0T
GNDPCI 18
VDDPCI 19
47 NS_SAS0C
46 GNDNS
VDD48 20
^_{48M_2x/100M_133M# 21}
45 VDDNS
44 NS_SRC1T
GND48 22
43 NS_SRC1C
GND96 23
42 NS_SRC0T
DOT96T 24
41 NS_SRC0C
DOT96C 25
40 IREF
AVDD96 26
39 GNDSRC
TEST_MODE 27
38 AVDD_SRC
CKPWRGD#/PD 28
37 VDDSRC
VDDSRC 29
36 SRC2T
SRC0T 30
SRC0C 31
35 SRC2C
34 SRC1T
GNDSRC 32
33 SRC1C
64-TSSOP
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldown
Spread Spectrum Control
SS_Enable
(B1 b0)
0
1
CPU, SRC &
PCI
OFF
ON
Power Group Pin Numbers
MLF
TSSOP
VDD GND VDD GND
Desc ription
57 56 3
2 14MHz PLL Analog
58 60 4
6 REF14M Output and Logic
64 61 10
7 25MHz XTAL
2, 9 1, 8 12, 19 11, 18 PCI Outputs and Logic
10 12 20 22 48MHz Output and Logic
16 13 26 23 96MHz PLL Analog, Output and Logic
19, 27 22 29, 37 32 SRC Outputs and Logic
28 29 38 39 SRC PLL Analog
35
41
47, 53
36 45
42 51
48 57,63
46 ^{Non-Spreading Differential Outputs & Logic}
52 NS-SAS/SRC PLL Analog
58 CPU Outputs and Logic
932SQ420 Power Down Functionality
CK PW RG D#/PD
1
0
Differential
Outputs
HI-Z¹
Single-ended
Outputs
Low
Runn ing
Single ended
Outputs w/Latch
Low²
1. Hi-Z on the differential outputs will result in both True and
Complement being low due to the termination network
2. These outputs are Hi-Z after VDD is applied and before the first
assertion of CKPWRGD #.
IDT® PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
2
932SQ420D
REV H 042012