841N254B Datasheet, PDF (21/24 Pages) Integrated Device Technology – FemtoClock NG Crystal-to-LVDS/ HCSL Clock Synthesizer

Package Outline and Package Dimensions
Package Outline - K Suffix for 32-Lead VFQFN
Ind exArea
N
To p View
S eating Plan e
A1
A_An_nv_vi_il_l
Si_Sn_ig_ngu_ula_lati_to_ion_n
or
Sa^Ow^Rn
Singulation
A3 ^L
E 2 _E2
2
(N -1)x e
(R ef.)
N
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
A
0. 08 C
e
(Ref.)
N &N
Odd
C
D2
2
D2
(Ref.)
N &N
Even
e (Ty p.)
2 _{If N & N}
1 ^{are Even}
2
(N -1)x e
(Re f.)
b
Th er mal
Ba se
841N254B Datasheet
Bottom View w/Type A ID
Bottom View w/Type C ID
2
2
1
1
CHAMFER
4
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
Symbol
N
A
A1
A3
b
N_D & N_E
D&E
D2 & E2
e
L
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Minimum
Nominal
32
0.80
0
0.25 Ref.
0.18
0.25
5.00 Basic
3.0
0.50 Basic
0.30
0.40
Maximum
1.00
0.05
0.30
8
3.3
0.50
Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
©2016 Integrated Device Technology, Inc.
21
Revision B, May 23, 2016