841N254B Datasheet, PDF(12/24 Page) Integrated Device Technology – FemtoClock NG Crystal-to-LVDS/ HCSL Clock Synthesizer

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841N254B Datasheet, PDF (12/24 Pages) Integrated Device Technology – FemtoClock NG Crystal-to-LVDS/ HCSL Clock Synthesizer

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841N254B Datasheet

Applications Information

Recommendations for Unused Input Pins

Inputs:

REF_CLK Input

For applications not requiring the use of the reference clock, it can be

left floating. Though not required, but for additional protection, a 1kï

resistor can be tied from the REF_CLK to ground.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1kï resistor can be tied from

XTAL_IN to ground.

LVCMOS Control Pins

All control pins have internal pulldowns; additional resistance is not

required but can be added for additional protection. A 1kï resistor

can be used.

Outputs:

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated

with 100ï across. If they are left floating, we recommend that there

is no trace attached.

Differential Outputs

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Interface to IDT S-RIO Switches

The 841N254B is designed for driving the differential reference clock

input (REF_CLK) of IDTâs S-RIO 1.3 and 2.0 switch devices. Both the

LVDS and the HCSL outputs of the ICS841N254BI have the low-jitter,

differential voltage and impedance characteristics required to provide

a high-quality 156.25MHz clock signal for both S-RIO 1.3 and 2.0

switch devices. Please refer to Figure 1A and Figure 1B for

suggested interfaces. The interfaces differ by the driving output,

LVDS and HCSL, and the corresponding source termination method.

In both Figure 1A and 1B, the AC-coupling capacitors are mandatory

by the IDT S-RIO switch devices. The differential REF_CLK input is

internally re-biased and AC-terminated. Both interface circuits are

optimized for 50ï transmission lines and generate the voltage swing

required to reliably drive the clock reference input of a IDT S-RIO

switch. Please refer to IDTâs S-RIO device datasheet for more details.

Figure 1A shows the recommended interface circuit for driving the

156.25MHz reference clock of an IDT S-RIO 2.0 switch by a LVDS

output (QA0, QA1) of the ICS841N254BI. The LVDS-to-differential

interface as shown in Figure 1A does not require any external

termination resistors: the ICS841N254BI driver contains an internal

source termination at QA0 and QA1. The differential REF_CLK input

contains an internal AC-termination (RL) and re-bias (VBIAS).

Figure 4B shows the interface circuit for driving the 156.25MHz

reference clock of an IDT S-RIO 2.0 switch by an HCSL output of the

841N254B (QB0, QB1): The HCSL-to-differential interface requires

external termination resistors (22...33ï and 50ï) for source

termination, which should be placed close the driver (QB0, QB1).

QAnï

LVDS nQAn

REF_CLK_Pï

T= 50ï ï

REF_CLK_N

VBIAS

RL + REF_CLK

QBnï

HCSL nQBn

22...33

49.9

REF_CLK_Pï

ï T= 50ï

49.9ï

REF_CLK_N

VBIAS

RL + REF_CLK

ICS841N254BI

IDT S-RIO 1.3, 2.0 Switch

Figure 1A. LVDS-to-S-RIO 2.0 Reference Clock Interfaceï

ICS841N254BI

IDT S-RIO 1.3, 2.0 Switch

Figure 1B. HCSL-to-S-RIO 2.0 Reference Clock Interface

Revision B, May 23, 2016

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