841N254B Datasheet, PDF(17/24 Page) Integrated Device Technology – FemtoClock NG Crystal-to-LVDS/ HCSL Clock Synthesizer

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

841N254B Datasheet, PDF (17/24 Pages) Integrated Device Technology – FemtoClock NG Crystal-to-LVDS/ HCSL Clock Synthesizer

◁

841N254B Datasheet

Schematic Layout

Figure 6 shows an example of 841N254B application schematic. In

this example, the device is operated at VDD = VDDOA = VDDOB = 3.3V.

The 12pF parallel resonant 25MHz crystal is used. The load capaci-

tance C1 = 5pF and C2 = 5pF are recommended for frequency accu-

racy. Depending on the parasitic of the printed circuit board layout,

these values might require a slight adjustment to optimize the fre-

quency accuracy. Crystals with other load capacitance specifications

can be used. This will require adjusting C1 and C2. For this device,

the crystal load capacitors are required for proper operation.

As with any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The 841N254B provides separate

power supplies to isolate any high switching noise from coupling into

the internal PLL.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1ÂµF capacitor in each power pin filter should be placed on the de-

vice side. The other components can be on the opposite side of the

PCB.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for a wide range of noise frequencies.

This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching

power supplies frequencies, it is recommended that component val-

ues be adjusted and if required, additional filtering be added. Addi-

tionally, good general design practices for power plane voltage

stability suggests adding bulk capacitance in the local area of all de-

vices.

The schematic example focuses on functional connections and is not

configuration specific. Refer to the pin description and functional ta-

bles in the datasheet to ensure that the logic control inputs are prop-

erly set.

L ogic Control Input E xamples

Set Logic

V DD Inp ut t o

'1'

RU1

S et Log ic

VDD Input to

'0'

RU2

N ot I ns t al l

To Logic

Input

pins

RD1

N ot I ns t all

To Logic

Input

pins

RD2

VD D

0.1u

VD D

VDDA

0.01u

10u

VD D

VDD

0.1u

Ro ~ 7 Ohm R 8 Zo = 50 Ohm

VDD

D riv er_LV C MOS

R EF _C LK

nOE A

0.1u

VD D

4 VD D A

5 nc

6 GND

7 R EF _C LK

nOEA

VD D

VD D O

IREF

GND

nQA0 21

QA0 20

VDDOA 19

nQA1 18

QA1

GND

R4 33

QB0

Zo = 50

R5 33

n Q B0

TL2

Zo = 50

TL3

R6 R7

50 50

Using for P CI Express

Add-In C ard

475

VDD=3.3V

VDDOA= VDDOB=3.3V

HCSL Term ina tion

Optional

R9 33

QB1

QB 1_33 Zo = 50

n Q A0

VDD O

R10 33

TL5

QA0

n Q B1

nQB1_33 Zo = 50

TL6

R11 R12

50 50

LV DS Termination

Using for PC I Express

Point-to-P oint

Connec tion

5pF

25M1 H2 p zF

XTAL_I N

XTA L_O U T

VD D

0.1u

5pF

QA1

Z o = 100 O hm D if f erent ial R 1

100

nQA 1

3.3V

BLM18BB 221SN 1

F errit e Bead C 10

C11 C17

0.1uF

10uF 0. 1uF 0. 1uF

VDDO

3. 3V

BLM18BB 221SN 1

VD D

F errit e Bead C 13

C14

C12

0.1uF

10uF 0. 1uF

Figure 6. 841N254B Application Schematic

Revision B, May 23, 2016

▷