ICS8745BI-21 Datasheet, PDF (20/21 Pages) Integrated Device Technology – Output frequency range

ICS8745BI-21 Data Sheet
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Revision History Sheet
Rev
Table
Page
Description of Change
B
T4D
5 LVDS DC Characteristics Table - modified VOS 0.90V min. to 1.05V min,
1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max.
T6
7
AC Characteristics Table - changed t_PD max limit from 3.9ns to 4.0ns.
C
12 Added Recommendations for Unused Input & Output Pins.
15 Added Power Considerations section.
Updated format throughout the datasheet.
1 Pin Assignment - corrected lineup of pin names.
T3A
3 Control Input Function Table - deleted “z” from 1st row of SEL3 column.
T 3B
4 PLL Bypass Function Table - deleted “z” from 1st row of SEL3 column
T4C
6 Differential DC Characteristics Table - updated NOTES.
C
T6
7 AC Characteristics Table - added thermal note.
10 Power Supply Filtering Technique - updated paragraph.
11 Updated Differential Clock Input Interface.
T10
17 Ordering Information Table - added “LF” marking. Deleted “ICS” prefix in Part/Order number
column.
Updated Header/Footer of datasheet.
1 Added 32 Lead VFQFN proposed pin assignment.
5 Absolute Maximum Ratings - added 32 Lead VFQN Package Thermal Impedance.
10 Updated Wiring the Differential Input to Accept Single-ended Levels.
12 Updated LVDS Output Termination.
D
13 Added VFQFN EPad Thermal Release section.
T7B
16 Added proposed 32 Lead VFQFN Thermal Resistance table.
T8B
17 Added proposed 32 Lead VFQFN theta ja table.
T9B
18 Added proposed 32 Lead VFQFN Package Outline and Dimensions.
T10
19 Ordering Information Table added proposed 32 Lead VFQFN ordering information.
Date
3/17/04
4/17/07
1/25/10
7/28/10
ICS8745BMI-21 REVISION D JULY 28, 2010
20
©2010 Integrated Device Technology, Inc.