ICS8745BI-21 Datasheet, PDF (2/21 Pages) Integrated Device Technology – Output frequency range

ICS8745BI-21 Data Sheet
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1
CLK
Input Pulldown Non-inverting differential clock input.
2
nCLK
Input
Pullup Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
3
MR
Input
Pulldown
causing the true output Q to go low and the inverted output nQ to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
4
nFBIN
Input
Pullup
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
5
FBIN
Input
Pulldown
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
6, 15,
19, 20
SEL2, SEL3,
SEL0 SEL1
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
7, 11
8, 9
V_DDO
nQFB/QFB
Power
Output
Output supply pins.
Differential feedback output pair. LVDS interface levels.
10, 14
GND
Power
Power supply ground.
12, 13
nQ/Q
Output
Differential output pair. LVDS interface levels.
16
V_DDA
Power
Analog supply pin.
17
PLL_SEL
Input
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.
18
V_DD
Power
Core supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
R_PULLUP
R_PULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS8745BMI-21 REVISION D JULY 28, 2010
2
©2010 Integrated Device Technology, Inc.