ICS8745BI-21 Datasheet, PDF (16/21 Pages) Integrated Device Technology – Output frequency range

ICS8745BI-21 Data Sheet
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8745BI-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8745BI-21 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{DD_MAX} * (I_{DD_MAX} + I_{DDA_MAX}) = 3.465V * (128mA + 18mA) = 506mW
• Power (outputs)_MAX = V_{DDO_MAX} * I_{DDO_MAX} = 3.465V * 62mA = 215mW
Total Power__MAX = 506mW + 215mW = 721mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 46.2°C/W per Table 7A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.721W * 46.2°C/W = 118.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7A. Thermal Resistance θ_JA for 20 Lead SOIC, Forced Convection
θ_JA vs. Air Flow
Linear Feet per Minute
0
200
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
500
57.5°C/W
36.8°C/W
Table 7B. Thermal Resistance θ_JA for 32 Lead VFQFN, Forced Convection
ED θ_JA vs. Air Flow
S _{Meters per Second}
0
PROPO ^{Multi-Layer PCB, JEDEC Standard Test Boards}
37.0°C/W
1
32.4°C/W
2.5
29.0°C/W
ICS8745BMI-21 REVISION D JULY 28, 2010
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©2010 Integrated Device Technology, Inc.