ICS8745BI-21 Datasheet, PDF (11/21 Pages) Integrated Device Technology – Output frequency range

ICS8745BI-21 Data Sheet
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both differential signals must meet the V_PP
and V_CMR input requirements. Figures 3A to 3F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
CLK
nCLK
Differential
R1
R2
84Ω
84Ω
Input
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
3.3V
3.3V
*R3 33Ω
Zo = 50Ω
Zo = 50Ω
*R4 33Ω
HCSL
R1
50Ω
*Optional – R3 and R4 can be 0Ω
CLK
nCLK
R2
50Ω
Differential
Input
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
120Ω
R4
120Ω
3.3V
CLK
R1
120Ω
R2
120Ω
nCLK
Differential
Input
Figure 3F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
ICS8745BMI-21 REVISION D JULY 28, 2010
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©2010 Integrated Device Technology, Inc.