ICS8745BI-21 Datasheet, PDF (14/21 Pages) Integrated Device Technology – Output frequency range

ICS8745BI-21 Data Sheet
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Schematic Example
The schematic of the ICS8745BI-21 layout example is shown in
Figure 6A. The ICS8745BI-21 recommended PCB board layout for
this example is shown in Figure 6B. This layout example is used as a
general guideline. The layout in the actual system will depend on the
selected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
3.3V
(155.52 MHz)
Zo = 50 Ohm
Zo = 50 Ohm
3.3V PECL Driver
SP = Space (i.e. not intstalled)
VDD
R8
R9
50
50
R10
50
U1
1
2
3
4
5
CLK
nCLK
MR
nFB_IN
SEL2
VDDO
6
7
8
9
10
FB_IN
SEL2
VDDO
nQFB
QFB
GND
R2
ICS8745B-21
100
20
SEL1
SEL0
VDDI
PLL_SEL
19
18
17
16
VDDA
SEL3
GND
Q
nQ
15
14
13
12
11
VDDO
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
VDDO
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
PLL_SEL
SEL0
SEL1
SEL2
SEL3
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
Bypass capacitors located
near the power pins
(U1-7)
(U1-11)
VDDO
C4
0.1uF
C2
0.1uF
VDD=3.3V
VDDO=3.3V
SEL[3:0] = 0101,
Divide by 2
C1
0.1uF
C11
0.01u
R7 VDD
10
C16
10u
(77.76 MHz)
+
R4
100
-
Zo = 100 Ohm Differential
LVDS_input
Figure 6A. ICS8745BI-21 LVDS Zero Delay Buffer Schematic Example
ICS8745BMI-21 REVISION D JULY 28, 2010
14
©2010 Integrated Device Technology, Inc.