ICS85408I Datasheet, PDF (2/16 Pages) Integrated Device Technology – Low Skew, 1-to-8, Differential-to-LVDS Clock

ICS85408I Datasheet
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
nQ6, Q6
nQ5, Q5
nQ4, Q4
Type
Output
Output
Output
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
7, 8
nQ3, Q3 Output
Differential output pair. LVDS interface levels.
9, 10
nQ2, Q2 Output
Differential output pair. LVDS interface levels.
11, 12
nQ1, Q1 Output
Differential output pair. LVDS interface levels.
13, 14
nQ0, Q0 Output
Differential output pair. LVDS interface levels.
15
16
17, 19, 20
18, 21
22
23, 24
nCLK
CLK
V_DD
GND
OE
nQ7, Q7
Input
Input
Power
Power
Input
Output
Pullup
Pulldown
Pullup
Inverting differential clock input.
Non-inverting differential clock input.
Positive supply pins.
Power supply ground.
Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH,
the outputs are enabled. When LOW, the outputs are in High-Impedance. LVCMOS /
LVTTL interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
C_PD
Power Dissipation Capacitance
(per output)
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
4
51
51
Maximum
Units
pF
pF
kΩ
kΩ
ICS85408BGI REVISION B JULY 2, 2009
2
©2009 Integrated Device Technology, Inc.