ICS85408I Datasheet, PDF (12/16 Pages) Integrated Device Technology – Low Skew, 1-to-8, Differential-to-LVDS Clock

ICS85408I Datasheet
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS85408I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85408I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The
following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)_MAX = V_{DD_MAX} * I_{DD_MAX} = 3.465V * 90mA = 311.85mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 70°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.312W * 70°C/W = 106.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θ_JA for 24 Lead TSSOP, Forced Convection
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
1
65.0°C/W
2.5
62°C/W
ICS85408BGI REVISION B JULY 2, 2009
12
©2009 Integrated Device Technology, Inc.