ICS85408I Datasheet, PDF (13/16 Pages) Integrated Device Technology – Low Skew, 1-to-8, Differential-to-LVDS Clock

ICS85408I Datasheet
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Reliability Information
Table 7. θ_JA vs. Air Flow Table for a 24 Lead TSSOP
θ_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
1
65.0°C/W
2.5
62°C/W
Transistor Count
The transistor count for ICS85408I is: 1821
Pin compatible with SN65LVDS104
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol Minimum Maximum
N
16
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS85408BGI REVISION B JULY 2, 2009
13
©2009 Integrated Device Technology, Inc.