ICS851S201I Datasheet, PDF (2/17 Pages) Integrated Device Technology – 2:1 Differential-to-HCSL Multiplexer with Low Input Level Alarm

ICS851S201I Data Sheet
2:1 DIFFERENTIAL-TO-HCSL MULTIPLEXER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
1
CLK0
Input
Pulldown
2
nCLK0
Input
Pullup/
Pulldown
3
CLK1
Input
Pulldown
4
nCLK1
Input
Pullup/
Pulldown
5, 13
V_DD
Power
6
LLAR
Input
Pulldown
7
8, 16
LLA
GND
Output
Power
Description
Non-inverting differential HCSL clock input.
Inverting differential HCSL clock input. V_DD/2 default when left floating.
Non-inverting differential HCSL clock input.
Inverting differential HCSL clock input. V_DD/2 default when left floating.
Positive supply pins.
Low Level Alarm Reset. When HIGH, resets LLA latch. Must be LOW to
allow LLA to set. LVCMOS/LVTTL interface levels.
Low Level Alarm. When HIGH, low level input has been detected on
selected differential input (latched).
Power supply ground.
9, 10
Q1, nQ1
Output
Differential output pair. HCSL interface levels.
11, 12
Q0, nQ0
Output
Differential output pair. HCSL interface levels.
14
IREF
Input
External fixed precision resistor (475from this pin to ground provides a
reference current used for differential current-mode Qx, nQx clock outputs.
15
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
R_PULLDOWN
R_PULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
k
ICS851S201CKI MAY 27, 2017
2
©2017 Integrated Device Technology, Inc.