ICS8344-01_07 Datasheet, PDF (2/15 Pages) Integrated Device Technology – Low Skew, 1-to-24 Differential-to-LVCMOS/LVTTL Fanout Buffer

ICS8344I-01 Data Sheet
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2, 5, 6,
7, 8, 11, 12
3, 9, 28,
34, 39, 45
4, 10,
14, 18, 27,
33, 40, 46
13
15, 19
16
17
20
21
22
23
24
25, 26, 29, 30,
31, 32, 35, 36
37, 38, 41, 42,
43, 44, 47, 48
Name
Q16, Q17, Q18,
Q19, Q20, Q21,
Q22, Q23
V_DDO
Type
Output
Power
Description
Single-ended clock outputs. 7Ω typical output Impedance.
LVCMOS/LVTTL interface levels.
Output supply pins.
GND
Power
Power supply ground.
CLK_SEL
V_DD
nCLK1
CLK1
nCLK0
CLK0
CLK_EN
Input
Power
Input
Input
Input
Input
Input
OE
Input
nc
Q0, Q1, Q2, Q3,
Q4, Q5, Q6, Q7
Q8, Q9, Q10,
Q11, Q12, Q13,
Q14, Q15
Unused
Output
Output
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pullup
Clock select input. When HIGH, selects CLK1, nCLK inputs, When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
Power supply pins.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Synchronizing control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q[0:23].
LVCMOS / LVTTL interface levels.
No connect.
Single-ended clock outputs. 7Ω typical output Impedance.
LVCMOS/LVTTL interface levels.
Single-ended clock outputs. 7Ω typical output Impedance.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
C_PD
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
R_PULLUP
R_PULLDOWN
R_OUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
V_DD = V_DDO = 3.465V
V_DD = V_DDO = 2.625V
V_DDO = 3.3V±5% or 2.5V±5%
Minimum
Typical
4
23
16
51
51
7
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
ICS8344AYI-01 REVISION A FEBRUARY 29, 2012
2
©2012 Integrated Device Technology, Inc.