ICS8344-01_07 Datasheet, PDF (1/15 Pages) Integrated Device Technology – Low Skew, 1-to-24 Differential-to-LVCMOS/LVTTL Fanout Buffer

Low Skew, 1-to-24
Differential-to-LVCMOS/LVTTL Fanout Buffer
ICS8344I-01
DATA SHEET
General Description
The ICS8344I-01 is a low voltage, low skew fanout buffer. The
ICS8344I-01 has two selectable clock inputs. The CLKx, nCLKx
pairs can accept most standard differential input levels. The
ICS8344I-01 is designed to translate any differential signal level to
LVCMOS/LVTTL levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased to 48 by
utilizing the ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock inputs
which also facilitate board level testing. The clock enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin. The
outputs are driven low when disabled. The ICS8344I-01 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V
output operating supply modes.
Guaranteed output and part-to-part skew characteristics make the
ICS8344I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
• Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
• Two selectable differential CLKx, nCLKx inputs
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following
input levels: LVDS, LVPECL, LVHSTL, HCSL
• Maximum output frequency: 100MHz
• Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
• Synchronous clock enable
• Additive phase jitter, RMS: 0.21ps (typical)
• Output skew: 200ps (maximum)
• Part-to-part skew: 900ps (maximum)
• Bank skew: 180ps (maximum)
• Propagation delay: 5ns (maximum)
• Output supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
• -40°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
CLK_SEL ^Pulldown
CLK0 ^Pulldown
nCLK0 ^Pullup
0
CLK1 ^Pulldown
nCLK1 ^Pullup
1
CLK_EN ^Pullup
OE ^Pullup
LE
Q
nD
8 _Q[0:7]
8 _Q[8:15]
8 _Q[16:23]
Pin Assignment
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
ICS8344I-01
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8344AYI-01 REVISION A FEBRUARY 29, 2012
1
©2012 Integrated Device Technology, Inc.