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| ICS8344-01_07 Datasheet, PDF (11/15 Pages) Integrated Device Technology – Low Skew, 1-to-24 Differential-to-LVCMOS/LVTTL Fanout Buffer | |||
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ICS8344I-01 Data Sheet
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8344I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8344I-01 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
⢠Power (core)MAX = VDD_MAX * IDD = 3.465V *95mA = 329.2mW
⢠Output Impedance ROUT Power Dissipation due to Loading 50⦠to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50⦠+ ROUT)] = 3.465V / [2 * (50⦠+ 7â¦)] = 30.4mA
⢠Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 7⦠* (30.4mA)2 = 6.47mW per output
⢠Total Power (ROUT) = 6.47mW * 24 = 155mW
Dynamic Power Dissipation at 100MHz
Power (100MHz) = CPD * Frequency * (VDD)2 = 16pF * 100MHz * (3.465V)2 = 19.2mW per output
Total Power (100MHz) = 19.2mW * 24 = 461mW
Total Power Dissipation
⢠Total Power
= Power (core)MAX + Power (ROUT) + Power (100MHz)
= 329.2mW + 155mW + 461mW
= 945.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 81.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.945W *53.9°C/W = 120.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 48 Lead LQFP, Forced Convection
θJA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
53.9°C/W
1
47.7°C/W
2.5
45.0°C/W
ICS8344AYI-01 REVISION A FEBRUARY 29, 2012
11
©2012 Integrated Device Technology, Inc.
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