845254 Datasheet, PDF (2/20 Pages) Integrated Device Technology – FemtoClock Crystal-to-3.3V, 2.5V

845254 Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-CML CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 2
3, 18
4
5, 6, 7, 8, 9, 16,
17, 19, 25, 32
10
11
12
13, 29
14,
15
20, 21
Name
nQ0, Q0
V_DD
nOE
nc
V_DDA
nBYPASS
REF_CLK
GND
XTAL_OUT,
XTAL_IN
FSEL0,
FSEL1
Type
Output
Power
Input Pulldown
Unused
Power
Input
Input
Power
Pullup
Pulldown
Input
Input Pulldown
Description
Differential clock output pair. CML interface levels.
Core supply pins.
Output enable pin. See Table 3E for function. LVCMOS/LVTTL interface levels.
Do not connect.
Analog supply pin.
PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Output frequency divider select enable pins. See Table 3C for function.
LVCMOS/LVTTL interface levels.
22
23, 24
REF_SEL
Q3, nQ3
Input
Output
Pulldown
PLL reference clock select pin. See Table 3A for function.
LVCMOS/LVTTL interface levels.
Differential clock output pair. CML interface levels.
26
27, 28
30, 31
FBSEL
nQ2, Q2
nQ1, Q1
Input
Output
Output
Pulldown ^{PLL feedback divider select pin. See Table 3B for function.}
LVCMOS/LVTTL interface levels.
Differential clock output pair. CML interface levels.
Differential clock output pair. CML interface levels.
NOTE: Pulldown and pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLDOWN Input Pulldown Resistor
R_PULLUP
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
845254 REVISION B 08/25/15
2
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