845254 Datasheet, PDF (15/20 Pages) Integrated Device Technology – FemtoClock Crystal-to-3.3V, 2.5V

845254 Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-CML CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the CML driver output pair. The CML output circuit and termination are
shown in Figure 6.
VDD
RL1
RL2
50
50
Q
nQ
V_output
Q1
Q2
I_load
External Loads
IC
Figure 6. CML Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations:
Power dissipation when the output driver is logic LOW:
Pd_L = I_Load * V_Output
= (V_{OUT_MAX} /R_L) * (V_{DD_MAX} – V_{OUT_MAX})
= (600mV/50) * (3.465V – 600mV)
= 34.38mW
Power dissipation when the output driver is logic HIGH:
Pd_H = I_Load * V_Output
= (0.025V/50) * (3.465V – 0.025V)
= 1.72mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 36.1mW
845254 REVISION B 08/25/15
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