845254 Datasheet, PDF (13/20 Pages) Integrated Device Technology – FemtoClock Crystal-to-3.3V, 2.5V

845254 Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-CML CLOCK GENERATOR
Schematic Example
Figure 5 shows an example of ICS845254I application schematic. In
this example, the device is operated at V_DD = 3.3V. The 18pF parallel
resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are
recommended for frequency accuracy. For different board layouts,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of CML terminations are shown in this
schematic.
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDD
OE
0.01uF
C5
U1
1
2
3
nQ0
Q0
4
5
6
7
8
VDD
OE
nc
nc
nc
nc
VDD
R4
10 C3
C4
10uF
VDD
Q1
Ro ~ 7 Ohm
VDDA
0.01uF
R6
43
Driv er_LVCMOS
nBY PASS
Zo = 50
Figure 5. 845254 Schematic Layout Example
FBSEL
Zo = 50 Ohm
Q0
R1
VDD 50
+
-
R2
Zo = 50 Ohm
50
nQ0
VDD=3.3V
nQ3
Q3
24
23
22
REF_SEL
FSEL1
FSEL0
nc
VDD
21
20
19
18
17
nc
nQ3
Q3
REF_SEL
FSEL1
FSEL0
VDD
CML Termination
Zo = 50 Ohm
Q3
C6
0.01uF
R3
VDD 50
+
X1 ^{21 58 Mp HF z}
C1
27pF
-
R5
Zo = 50 Ohm
50
nQ3
C2
27pF
845254 REVISION B 08/25/15
13
©2015 Integrated Device Technology, Inc.