ICS8543I Datasheet, PDF (13/17 Pages) Integrated Device Technology – Four differential LVDS output pairs

ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8543I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8543I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{DD_MAX} * I_{DD_MAX} = 3.465V * 50mA = 173.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.173W * 73.2°C/W = 97.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6. Thermal Resitance _JA for 20 Lead TSSOP, Forced Convection
_JA by Velocity
Linear Feet per Minute
0
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
ICS8543BGI REVISION E NOVEMBER 15, 2012
13
©2012 Integrated Device Technology, Inc.