ICS8543I Datasheet, PDF (11/17 Pages) Integrated Device Technology – Four differential LVDS output pairs

ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both signals must meet the V_PP and V_CMR input
requirements. Figures 4A to 4F show interface examples for the S
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 4A. PCLK/nPCLK Input Driven by a
CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84Ω
84Ω
Input
Figure 4B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125 125
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 4C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
LVPECL
Input
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 4E. PCLK/nPCLK Input Driven by an
SSTL Driver
ICS8543BGI REVISION E NOVEMBER 15, 2012
Figure 4F. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
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©2012 Integrated Device Technology, Inc.