ICS94201 Datasheet, PDF (9/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94201
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with the wrong spread percentage and/or group to group divider ratio
programmed into bytes 16-20 could be unstable. Step 3 & 7 assure the correct spread and gear ratio.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow.
Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. Users can also utilize software utility provided to program the VCO frequency from ICS Application Engineering.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spread amount desired.
See Application note for software support.
Byte 16: Spread Sectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
X Spread Spectrum Bit7
X Spread Spectrum Bit6
X Spread Spectrum Bit5
X Spread Spectrum Bit4
X Spread Spectrum Bit3
X Spread Spectrum Bit2
X Spread Spectrum Bit1
X Spread Spectrum Bit0
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 17: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
X Divider control Bit26
0 Divider control Bit25
X Divider control Bit24
X Spread Spectrum Bit12
X Spread Spectrum Bit11
X Spread Spectrum Bit10
X Spread Spectrum Bit9
X Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 18: Output Dividers Control Register
Byte 19: Output Dividers Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
X Output Divider MUX Control Bit7
X Output Divider MUX Control Bit6
X Output Divider MUX Control Bit5
X Output Divider MUX Control Bit4
X Output Divider MUX Control Bit3
X Output Divider MUX Control Bit2
X Output Divider MUX Control Bit1
X Output Divider MUX Control Bit0
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
X Output Divider MUX Control Bit15
X Output Divider MUX Control Bit14
X Output Divider MUX Control Bit13
X Output Divider MUX Control Bit12
X Output Divider MUX Control Bit11
X Output Divider MUX Control Bit10
X Output Divider MUX Control Bit9
X Output Divider MUX Control Bit8
Note: Changing bits in these registers results in frequency
divider ratio changes. Incorrect configuration of
group gear ratio can cause system malfunction.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the harware (latch inputs FS[0:4]) or IIC (Byte 0 bit [1:7]) setting. Be sure to read
back and re-write the values of these 5 registers when VCO frequency change is desired for the first pass.
9