ICS94201 Datasheet, PDF (1/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

Integrated
Circuit
Systems, Inc.
ICS94201
Programmable System Frequency Generator for PII/III™
Recommended Application:
810/810E and Solano (815) type chipset
Output Features:
• 2 - CPUs @ 2.5V
• 13 - SDRAM @ 3.3V
• 3 - 3V66 @ 3.3V
• 8 - PCI @3.3V
• 1 - 24/48MHz@ 3.3V
• 1 - 48MHz @ 3.3V fixed
• 1 - REF @3.3V, 14.318MHz
Features:
• Programmable ouput frequency.
• Programmable ouput rise/fall time for PCI
and SDRAM clocks.
• Programmable 3V66 to PCI skew.
• Spread spectrum for EMI control
with programmable spread percentage.
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Support power management through PD#.
• Uses external 14.318MHz crystal.
• FS pins for frequency select
Key Specifications:
• CPU Output Jitter: <250ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps
• CPU Output Skew: <175ps
• PCI Output Skew: <500ps
• 3V66 Output Skew <175ps
• For group skew timing, please refer to the
Group Timing Relationship Table.
Pin Configuration
VDDREF
1
X1
2
X2
3
GNDREF
4
GND3V66
5
3V66-0
6
3V66-1
7
3V66-2
8
VDD3V66
9
VDDPCI
10
1_{*(FS0)PCICLK0}
11
1_{*(FS1)PCICLK1}
12
1_{*(SEL24_48#)PCICLK2}
13
GNDPCI
14
PCICLK3
15
PCICLK4
16
PCICLK5
17
VDDPCI
18
PCICLK6
19
PCICLK7
20
GNDPCI
21
PD#
22
SCLK
23
SDATA
24
VDDSDR
25
SDRAM11
26
SDRAM10
27
GNDSDR
28
56
REF0(FS4)*¹
55
VDDLAPIC
54
IOAPIC
53
VDDLCPU
52
CPUCLK0
51
CPUCLK1
50
GNDLCPU
49
GNDSDR
48
SDRAM0
47
SDRAM1
46
SDRAM2
45
VDDSDR
44
SDRAM3
43
SDRAM4
42
SDRAM5
41
GNDSDR
40
SDRAM6
39
SDRAM7
38
SDRAM_F
37
VDDSDR
36
GND48
35
24_48MHz(FS2)*
34
48MHz(FS3)*¹
33
VDD48
32
VDDSDR
31
SDRAM8
30
SDRAM9
29
GNDSDR
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
X1
XTAL
X2
OSC
PLL1
Spread
Spectrum
FS[4:0]
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
24_48MHz
REF0
2 ^{CPUCLK [1:0]}
12 ^{SDRAM [11:0]}
SDRAM_F
IOAPIC
PCICLK [7:0]
8
3V66 [2:0]
3
94201 Rev A - 05/24/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.