ICS94201 Datasheet, PDF (11/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94201
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Group Timing Relationship Table¹
Group
CPU to SDRAM
CPU to 3V66
SDRAM to 3V66
3V66 to PCI
PCI to IOAPIC
USB & DOT
CPU 66 MHz
SDRAM 100 MHz
Offset Tolerance
2.5 ns
500 ps
7.5 ns
500 ps
0.0 ns
500 ps
1.5-3.5ns 500 ps
0.0 ns
1.0 ns
Asynch
N/A
CPU 100 MHz
SDRAM 100 MHz
Offset Tolerance
5.0 ns
500 ps
5.0 ns
500 ps
0.0 ns
500 ps
1.5-3.5ns 500 ps
0.0 ns
1.0 ns
Asynch
N/A
CPU 133 MHz
SDRAM 100 MHz
Offset Tolerance
0.0 ns
500 ps
0.0 ns
500 ps
0.0 ns
500 ps
1.5-3.5ns 500 ps
0.0 ns
1.0 ns
Asynch
N/A
CPU 133 MHz
SDRAM 133 MHz
Offset Tolerance
3.75 ns 500 ps
0.0 ns
500 ps
3.75 ns 500 ps
1.5-3.5ns 500 ps
0.0 ns
1.0 ns
Asynch
N/A
1_{Guaranteed by design, not 100% tested in production.}
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5%, V_DDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating Supply
Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
I_DD3.3OP
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up resistors
V_IN = 0 V; Inputs with pull-up resistors
C_L = max cap loads;
CPU=66-133 MHz, SDRAM=100 MHz
CPU=133 MHz, SDRAM=133 MHz
2
V_SS-0.3
-5
-5
-200
V_DD+0.3
0.8
5
334
350
465
500
I_DD2.5OP C_L = max cap loads;
20
70
Powerdown Current I_DD3.3PD C_L = 0 pF; Input address to VDD or GND
280
600
Input Frequency
F_i
V_DD = 3.3 V
14.318
Pin Inductance
L_pin
7
C_IN
Logic Inputs
5
Input Capacitance¹
C_OUT Output pin capacitance
6
C_INX
X1 & X2 pins
27
45
Transition time¹
T_trans To 1st crossing of target frequency
3
Settling time¹
T_s
From 1st crossing to 1% target frequency
3
Clk Stabilization¹
T_STAB From V_DD = 3.3 V to 1% target frequency
3
Delay¹
t_PZH,t_PZL Output enable delay (all outputs)
t_PHZ,t_PLZ Output disable delay (all outputs)
1
1
10
10
1_{Guaranteed by design, not 100% tested in production.}
UNITS
V
V
µ^A
µ^A
mA
µ^A
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
11