ICS94201 Datasheet, PDF (10/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94201
Byte 20: Output Dividers Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
X Output Divider MUX Control Bit23
X Output Divider MUX Control Bit22
X Output Divider MUX Control Bit21
X Output Divider MUX Control Bit20
X Output Divider MUX Control Bit19
X Output Divider MUX Control Bit18
X Output Divider MUX Control Bit17
X Output Divider MUX Control Bit16
Note: Changing bits in these registers results in
frequency divider ratio changes. Incorrect
configuration of group gear ratio can cause
system malfunction.
Byte 22: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
1 3V66 to PCI Skew Bit3
0 3V66 to PCI Skew Bit2
0 3V66 to PCI Skew Bit1
1 3V66 to PCI Skew Bit0
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
Note: Default 3V66 to PCI skew is 2.5ns bit [7:4]=1001.
Each increment or decrement of bit 4 to 7 will
introduce 100ps delay or advance on all PCI
clocks.
Byte 24: Output Rise/Fall Time Select Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
0 (Reserved)
0 REF 0=Normal, 1=Weak
0 24,48Mhz 0=Normal, 1=Weak
0 (Reserved)
0 PCI 0=Normal, 1=Weak
0 3V66 0=Normal, 1=Weak
0 SDRAM 0=Normal, 1=Weak
0 (Reserved)
Byte 21: ICS Reserved Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
0 (Reserved)
Description
Note: This is an unused register. Writing to this register will
not affect device performance or functionality.
Byte 23: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
0
0
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
3V66 to IOAPIC Skew Bit 3
3V66 to IOAPIC Skew Bit 2
3V66 to IOAPIC Skew Bit 1
3V66 to IOAPIC Skew Bit 0
Note: Default 3V66 to IOAPIC skew is 2.5ns bit [3:0]=0111.
Each increment or decrement of bit 4 to 7 will introduce
100ps delay or advance on all IOAPIC clocks.
Notes:
1. PWD = Power on Default
2.
The power on default for
(latch inputs FS[0:4]) or
Ib^{2yCte(B16y-t2e00}
depends on the hardware
bit [1:7]) setting. Be sure
to read back and re-write the values of these 5 registers when
VCO frequency change is desired for the first pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is
intended, Byte 21-24 will lose their default power up value.
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