ICS94201 Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94201
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
-
X FS3#
-
X FS0#
-
X FS2#
35
1 24MHz
-
1 (Reserved)
34
1 48MHz
-
1 (Reserved)
38
1 SDRAM_F
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
20
1 PCICLK7
19
1 PCICLK6
17
1 PCICLK5
16
1 PCICLK4
15
1 PCICLK3
13
1 PCICLK2
12
1 PCICLK1
11
1 PCICLK0
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
39
1 SDRAM7
40
1 SDRAM6
42
1 SDRAM5
43
1 SDRAM4
44
1 SDRAM3
46
1 SDRAM2
47
1 SDRAM1
48
1 SDRAM0
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
8
1 3V66_2
6
1 3V66_0
7
1 3V66_1
-
X FS4#
54
1 IOAPIC
-
X FS1#
51
1 CPUCLK1
52
1 CPUCLK0
Byte 5: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
-
1 (Reserved)
-
1 (Reserved)
-
1 (Reserved)
-
1 (Reserved)
26
1 SDRAM11
27
1 SDRAM10
30
1 SDRAM9
31
1 SDRAM8
Byte 6: Byte Count Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
-
0 Reserved (Note)
-
0 Reserved (Note)
-
0 Reserved (Note)
-
0 Reserved (Note)
-
0 Reserved (Note)
-
1 Reserved (Note)
-
1 Reserved (Note)
-
0 Reserved (Note)
Note: Writing to this register will configure byte count and
how many bytes will be read back, default is 6 bytes.
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
6