ICS8735-01 Datasheet, PDF (9/17 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8735-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_CC, V_CCA, and V_CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 4 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each V pin.
CCA
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
3.3V
V_CC
.01µF 10Ω
V_CCA
.01µF
10µF
FIGURE 4. POWER SUPPLY FILTERING
LAYOUT GUIDELINE
The schematic of the ICS8735-01 layout example is shown in
Figure 5A. The ICS8735-01 recommended PCB board layout
for this example is shown in Figure 5B. This layout example is
used as a general guideline. The layout in the actual system will
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
VCC
SP = Space (i.e. not intstalled)
RU2
SP
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
CLK_SEL
PLL_SEL
SEL0
SEL1
SEL2
SEL3
SEL[3:0] = 0101,
Divide by 2
VCCA
C11
0.01u
R7 VCC
10
C16
10u
(77.76 MHz)
RD2
1K
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
VCC
VCCO
Zo = 50 Ohm
Zo = 50 Ohm
+
-
LVPECL_input
3.3V
(155.52 MHz)
Zo = 50 Ohm
SEL0
SEL1
Zo = 50 Ohm
3.3V PECL Driver
CLK_SEL
R8
R9
50
50
R10
50
SEL2
U1
1
2 ^SEL0
3
4
5
6
7
8
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
8735-01
24
VCCO ₂₃
Q3
nQ3
Q2
nQ2
Q1
nQ1
VCCO
22
21
20
19
18
17
R2
R1
50
50
R3
50
R5
R4
50
50
Output
R6 Termination
50 _Example
Bypass capacitor located near the power pins
(U1-9)
(U1-32)
VCC
VCC=3.3V
C1
0.1uF
C6
0.1uF
VCCO=3.3V
(U1-16)
(U1-17) (U1-24) (U1-25)
VCCO
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
8735AY-01
FIGURE 5A. ICS8735-01 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
9