ICS8735-01 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1
SEL0 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
2
SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
3
CLK0 Input Pulldown Non-inverting differential clock input.
4
nCLK0 Input Pullup Inverting differential clock input.
5
CLK1 Input Pulldown Non-inverting differential clock input.
6
nCLK1 Input Pullup Inverting differential clock input.
7
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1.
When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
8
MR
Input
Pulldown
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the otuputs are enabled.
LVCMOS / LVTTL interface levels.
9, 32
10
V_CC
nFB_IN
Power
Input
Core supply pins.
Pullup Feedback input to phase detector for regenerating clocks with "zero delay".
11
FB_IN Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
12
SEL2 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
13, 28
14, 15
V_EE
Power
nQ0, Q0 Output
Negative supply pins.
Differential output pair. LVPECL interface levels.
16, 17,
24, 25
V_CCO
Power
Output supply pins.
18, 19 nQ1, Q1 Output
Differential output pair. LVPECL interface levels.
20, 21 nQ2, Q2 Output
Differential output pair. LVPECL interface levels.
22, 23 nQ3, Q3 Output
Differential output pair. LVPECL interface levels.
26, 27 nQ4, Q4 Output
Differential output pair. LVPECL interface levels.
29
SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
30
V_CCA
Power
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
31 PLL_SEL Input Pullup When LOW, selects reference clock.When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8735AY-01
www.icst.com/products/hiperclocks.html
2
REV. F NOVEMBER 12, 2004