ICS8735-01 Datasheet, PDF (6/17 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
V_CC,
V_CCA,
V_CCO
LVPECL
V_EE
SCOPE
Qx
nQx
-1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
V_CC
nCLK0,
nCLK1
V
PP
CLK0,
CLK1
Cross Points
V_EE
DIFFERENTIAL INPUT LEVEL
V
CMR
nQx
Qx
nQy
Qy
t sk(o)
OUTPUT SKEW
Clock
20%
Outputs
80%
t_R
OUTPUT RISE/FALL TIME
nCLK0,
nCLK1
CLK0,
CLK1
nQ0:nQ4
Q0:Q4
t_PD
PROPAGATION DELAY
8735AY-01
nQ0:nQ4
Q0:Q4
tcycle n
➤
tcycle n+1
➤
80%
t_F
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
nQ0:nQ4
V_{SW I N G}
20%
Q0:Q4
Pulse Width
t
PERIOD
odc = ^{t PW}
t _PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nCLK0,
nCLK1
V_OH
CLK0,
CLK1
V_OL
nFB_IN
V_OH
FB_IN
V_OL
➤ t (Ø)
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t (Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PHASE JITTER & STATIC PHASE OFFSET
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
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