ICS8735-01 Datasheet, PDF (12/17 Pages) Integrated Circuit Systems – 1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8735-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
V
CCO
Q1
V_OUT
RL
50
V_CCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
• For logic high, V = V = V
– 1.0V
OUT
OH_MAX
CCO_MAX
(V
- V ⁾ = 1.0V
CCO_MAX OH_MAX
• For logic low, V = V = V
– 1.7V
OUT
OL_MAX
CCO_MAX
(V
- V ⁾ = 1.7V
CCO_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ^))/R ] * (V
-V )=
OH_MAX
CCO_MAX
L
CCO_MAX OH_MAX
CCO_MAX OH_MAX
L
CCO_MAX OH_MAX
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ^))/R ] * (V
-V )=
OL_MAX
CCO_MAX
L
CCO_MAX OL_MAX
CCO_MAX OL_MAX
L
CCO_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8735AY-01
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12
REV. F NOVEMBER 12, 2004