ICS87004 Datasheet, PDF (9/14 Pages) Integrated Circuit Systems – 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87004 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V , V , and V
DD DDA
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each V .
DDA
3.3V
V_DD
.01µF 10Ω
V
DDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLKx
nCLKx
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87004AG
www.icst.com/products/hiperclocks.html
9
REV. A JUNE 16, 2004