ICS87004 Datasheet, PDF (1/14 Pages) Integrated Circuit Systems – 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87004 is a highly versatile 1:4 Differential-
ICS
to-LVCMOS/LVTTL Clock Generator and a mem-
HiPerClockS™ _{ber of the HiPerClockS™ family of High Perfor-}
mance Clock Solutions from ICS. The ICS87004
has two selectable clock inputs. The CLK0, nCLK0
and CLK1, nCLK1 pairs can accept most standard differential
input levels. Internal bias on the nCLK0 and nCLK1 inputs
allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL.
The ICS87004 has a fully integrated PLL and can be configured
as zero delay buffer, multiplier or divider and has an input and
output frequency range of 15.625MHz to 250MHz. The refer-
ence divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-
input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The exter-
nal feedback allows the device to achieve “zero delay” between
the input clock and the output clocks. The PLL_SEL pin can be
used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
BLOCK DIAGRAM
FEATURES
• 4 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Internal bias on nCLK0 and nCLK1 to support
LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 45ps (maximum)
• Static phase offset: 50 ± 125ps (3.3V ± 5%)
• Full 3.3V or 2.5V operating supply
• 5V tolerant inputs
• Lead-Free package available
• Industrial temperature information available upon request
PIN ASSIGNMENT
PLL_SEL
÷2, ÷4, ÷8, ÷16,
÷32, ÷64, ÷128
0
CLK0
nCLK0
0
1
CLK1
nCLK1
1
PLL
CLK_SEL
FB_IN
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0
GND 1
24 Q1
Q0
Q0 2
2 3 VDDO
VDDo 3
22 Q2
Q1
SEL0 4
SEL1 5
21 GND
20 Q3
SEL2 ⁶
1 9 VDDO
Q2
SEL3 ⁷
18 MR
CLK_SEL 8
17 FB_IN
VDD ⁹
16 _{PLL_SEL}
Q3
CLK0 ^{10 15} CLK1
nCLK0 ^{11 14} nCLK1
GND ^{12 13} VDDA
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
G Package
Top View
SEL1
SEL2
SEL3
MR
87004AG
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 16, 2004