ICS87004 Datasheet, PDF (6/14 Pages) Integrated Circuit Systems – 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
TABLE 5A.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
V
DDO
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
15.625
250
t_PD
Propagation Delay, CLK0, nCLK0
NOTE 1
CLK1, nCLK1
PLL_SEL = 0V
f ≤ 250MHz, Qx ÷ 2
5
6
t(Ø)
tsk(o)
Static Phase Offset;
NOTE 2, 4
Output Skew;
NOTE 3, 4
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 3.3V
f_REF ≤ 167MHz, Qx ÷ 1
PLL_SEL = 0V
-75
50
175
40
50
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4
f_OUT > 40MHz
30
45
t_L
PLL Lock Time
1
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
400
800
40
50
60
NOTE 1: Measured from the differential input crossing point to the output at V_DDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ms
ps
%
TABLE 5B.
AC
CHARACTERISTICS,
V=
DD
V=
DDA
V
DDO
= 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Output Frequency
15.625
250
t
PD
Propagation Delay, CLK0, nCLK0
NOTE 1
CLK1, nCLK1
PLL_SEL = 0V
f ≤ 250MHz, Qx ÷ 2
5.3
6.7
t(Ø)
tsk(o)
Static Phase Offset;
NOTE 2, 4
Output Skew;
NOTE 3, 4
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 2.5V
f_REF ≤ 167MHz, Qx ÷ 1
PLL_SEL = 0V
-175
-25
125
40
45
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4
f_OUT > 40MHz
35
45
t_L
t_R / t_F
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
1
400
700
44
50
56
NOTE 1: Measured from the differential input crossing point to the output at V_DDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
MHz
ns
ps
ps
ps
ms
ps
%
87004AG
www.icst.com/products/hiperclocks.html
6
REV. A JUNE 16, 2004