ICS87004 Datasheet, PDF (4/14 Pages) Integrated Circuit Systems – 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
Inputs, V_I
Outputs, V_O
Package Thermal Impedance, θ_JA
Storage Temperature, T_STG
4.6V
-0.5V to V_DD + 0.5 V
-0.5V to V_DDO + 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE
4A.
POWER
SUPPLY
DC
CHARACTERISTICS,
V =V =V
DD
DDA
DDO
=
3.3V±5%, TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical
V_DD
V_DDA
V_DDO
I_DD
I_DDA
I
DDO
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.3
3.135
3.3
3.135
3.3
Maximum
3.465
3.465
3.465
100
16
6
Units
V
V
V
mA
mA
mA
TABLE
4B.
LVCMOS
/
LVTTL
DC
CHARACTERISTICS,
V =V =V
DD
DDA
DDO
=
3.3V±5%
OR
2.5V±5%, TA
=
0°C TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical
V_IH
Input
High Voltage
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
2
V_IL
Input
Low Voltage
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
-0.3
CLK_SEL, MR, FB_IN,
V_DD = V_IN = 3.465V,
I_IH
Input
SEL0, SEL1, SEL2, SEL3
High Current
PLL_SEL
V_DD = V_IN = 2.625V
V_DD = V_IN = 3.465V,
V_DD = V_IN = 2.625V
I_IL
Input
Low Current
CLK_SEL, MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
PLL_SEL
V_DD = 3.465V, V_IN = 0V,
V_DD = 2.625V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V,
-5
-150
V_DD = 2.625V, V_IN = 0V
V_OH
Output High Voltage; NOTE 1
V_DDO = 3.465V
2.6
V_DDO = 2.625V
1.8
V_OL
Output Low Voltage; NOTE 1
V_DDO = 3.465V or 2.625V
NOTE 1: Outputs terminated with 50Ω to V_DDO/2. In the Parameter Measurement Information Section,
see Output Load Test Circuit Diagrams.
Maximum
V_DD + 0.3
0.8
150
5
0.5
Units
V
V
µA
µA
µA
µA
V
V
V
87004AG
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 16, 2004